Bonding technologies for chip level and wafer level 3D integration
- Katsuyuki Sakuma
- Spyridon Skordas
- et al.
- 2014
- ECTC 2014
Conference paper
Publications
22 results for Subramanian Iyer
Modeling and characterization of gate leakage in high-K metal gate technology-Based embedded DRAM
- Mohit Bajaj
- Rajan K. Pandey
- et al.
- 2013
- IEEE T-ED
PaperCopper through silicon via (TSV) for 3D integration
- C. Kothandaraman
- B. Himmel
- et al.
- 2012
- IRPS 2012
Conference paperPerformance analysis and modeling of deep trench decoupling capacitor for 32 nm high-performance SOI processors and beyond
- Balaji Jayaraman
- Sneha Gupta
- et al.
- 2012
- ICICDT 2012
Conference paper3D copper TSV integration, testing and reliability
- Mukta Farooq
- T. Graves-Abe
- et al.
- 2011
- IEDM 2011
Conference paper3D integration review
- Mukta G. Farooq
- Subramanian S. Iyer
- 2011
- Science China Information Sciences
ReviewA 0.039um2 high performance eDRAM cell based on 32nm high-K/metal SOI technology
- Nauman Z. Butt
- Kevin McStay
- et al.
- 2010
- IEDM 2010
Conference paperThree dimensional integration - Memory applications
- S.S. Iyer
- 2009
- IEEE International SOI Conference 2009
Conference paperScaling deep trench based eDRAM on SOI to 32nm and beyond
- G. Wang
- D. Anand
- et al.
- 2009
- IEDM 2009
Conference paperProcess-design considerations for three dimensional memory integration
- S.S. Iyer
- T. Kirihata
- et al.
- 2009
- VLSI Technology 2009
Conference paper