ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08μm2 SRAM cell
- Kangguo Cheng
- A. Khakifirooz
- et al.
- 2011
- VLSI Circuits 2011
Conference paper
Publications
51 results for Arvind Kumar
ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08μm2 SRAM cell
- Kangguo Cheng
- A. Khakifirooz
- et al.
- 2011
- VLSI Technology 2011
Conference paperSub-25nm FinFET with advanced fin formation and short channel effect engineering
- Tenko Yamashita
- Veeraraghvan S. Basker
- et al.
- 2011
- VLSI Technology 2011
Conference paperUltra-thin Body and BOX (UTBB) device for aggressive scaling of CMOS technology
- Q. Liu
- A. Yagishita
- et al.
- 2011
- CSTIC 2011
Conference paperImpact of lateral asymmetric channel doping on 45-nm-technology N-Type SOI MOSFETs
- Hasan M. Nayfeh
- Nivo Rovedo
- et al.
- 2009
- IEEE Transactions on Electron Devices
PaperFDSOI CMOS with dual backgate control for performance and power modulation
- Jeng-Bang Yau
- Jin Cai
- et al.
- 2009
- VLSI-TSA 2009
Conference paperChallenges and solutions of FinFET integration in an SRAM cell and a logic circuit for 22 nm node and beyond
- H. Kawasaki
- V.S. Basker
- et al.
- 2009
- IEDM 2009
Conference paperFinFET resistance mitigation through design and process optimization
- Cindy Wang
- Josephine Chang
- et al.
- 2009
- VLSI-TSA 2009
Conference paperGate length and performance scaling of undoped-body extremely thin SOI MOSFETs
- Amlan Majumdar
- Xinlin Wang
- et al.
- 2009
- IEEE Electron Device Letters
PaperSOI series MOSFET for embedded high voltage applications and soft-error immunity
- Jin Cai
- Tak Ning
- et al.
- 2008
- IEEE International SOI Conference 2008
Conference paper