22nm technology yield optimization using multivariate 3D virtual fabrication
- B. Cipriany
- B. Jagannathan
- et al.
- 2013
- SISPAD 2013
Conference paper
Publications
13 results for M. Kumar
22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL
- S. Narasimha
- P. Chang
- et al.
- 2012
- IEDM 2012
Conference paperHigh performance 32nm SOI CMOS with high-k/metal gate and 0.149μm 2 SRAM and ultra low-k back end with eleven levels of copper
- B. Greene
- Q. Liang
- et al.
- 2009
- VLSI Technology 2009
Conference paperImproving yields of high performance 65 nm chips with sputtering top surface of dual stress liner
- Huilong Zhu
- Daewon Yang
- et al.
- 2007
- VLSI Technology 2007
Conference paperSymmetric vertical parallel plate capacitors for on-chip RF circuits in 65-nm SOI technology
- Daeik Kim
- Jonghae Kim
- et al.
- 2007
- IEEE Electron Device Letters
PaperManufacturable parasitic-aware circuit-level FETs in 65-nm SOI CMOS technology
- Daeik Kim
- Jonghae Kim
- et al.
- 2007
- IEEE Electron Device Letters
PaperA 70GHz manufacturable complementary LC-VCO with 6.14GHz tuning range in 65nm SOI CMOS
- Daeik D. Kim
- Jonghae Kim
- et al.
- 2007
- ISSCC 2007
Conference paperRTA-driven intra-die variations in stage delay, and parametric sensitivities for 65nm technology
- I. Ahsan
- N. Zamdmer
- et al.
- 2006
- VLSI Technology 2006
Conference paperHigh performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell
- E. Leobandung
- H. Nayakama
- et al.
- 2005
- VLSI Technology 2005
Conference paperVertical SiGe-base bipolar transistors on CMOS-compatible SOI substrate
- Jin Cai
- Mahender Kumar
- et al.
- 2003
- BCTM 2003
Conference paper