Optimal UTB FD/SOI device structure using thin BOX for sub-50-nm SRAM design
- Saibal Mukhopadhyay
- Keunwoo Kim
- et al.
- 2006
- IEEE Electron Device Letters
Paper
Publications
109 results for David J. Frank
Enabling SOI-based assembly technology for three-dimensional (3D) integrated circuits (ICs)
- A. Topol
- D.C. La Tulipe
- et al.
- 2005
- IEDM 2005
Conference paperAssembly technology for three dimensional integrated circuits
- A. Topol
- D.C. La Tulipe
- et al.
- 2005
- VMIC 2005
Conference paperSRAM Cell Design for Stability Methodology
- Clement Wann
- Robert Wong
- et al.
- 2005
- VLSI Technology 2005
Conference paperAggressively scaled (0.143 μm 2) 6T-SRAM cell for the 32 nm node and beyond
- D. Fried
- J. Hergenrother
- et al.
- 2004
- IEDM 2004
Conference paperUniversal tunneling behavior in technologically relevant P/N junction diodes
- Paul M. Solomon
- Jason Jopling
- et al.
- 2004
- Journal of Applied Physics
PaperFrequency dependent characterization of transport properties in carbon nanotube transistors
- J. Appenzeller
- D.J. Frank
- 2004
- Applied Physics Letters
PaperHigh-Frequency Response in Carbon Nanotube Field-Effect Transistors
- David J. Frank
- Joerg Appenzeller
- 2004
- IEEE Electron Device Letters
PaperTunnel Current Measurements on P/N Junction Diodes and Implications for Future Device Design
- Paul M. Solomon
- David J. Frank
- et al.
- 2003
- IEDM 2003
Conference paperGrowth and scaling of oxide conduction after breakdown
- Barry P. Linder
- James H. Stathis
- et al.
- 2003
- IRPS 2003
Conference paper