Publications

35 results for Renee Mo

First demonstration of high-Ge-content strained-Si_1-xGe_x (x=0.5) on insulator PMOS FinFETs with high hole mobility and aggressively scaled fin dimensions and gate lengths for high-performance applications
- - Pouya Hashemi
  - Karthik Balakrishnan
  - et al.
- 2014
- IEDM 2014
Conference paper
High performance 32nm SOI CMOS with high-k/metal gate and 0.149μm ² SRAM and ultra low-k back end with eleven levels of copper
- - B. Greene
  - Q. Liang
  - et al.
- 2009
- VLSI Technology 2009
Conference paper
Gate length scaling and high drive currents enabled for high performance SOI technology using high-κ/metal gate
- - K. Henson
  - H. Bu
  - et al.
- 2008
- IEDM 2008
Conference paper
A cost effective 32nm high-K/metal gate CMOS technology for low power applications with single-metal/gate-first process
- - X. Chen
  - S. Samavedam
  - et al.
- 2008
- VLSI Technology 2008
Conference paper
High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing
- - M. Chudzik
  - B. Doris
  - et al.
- 2007
- VLSI Technology 2007
Conference paper
Dual stress liner enhancement in hybrid orientation technology
- - C. Sheraw
  - M. Yang
  - et al.
- 2005
- VLSI Technology 2005
Conference paper
High performance CMOS bulk technology using direct silicon bond (DSB) mixed crystal orientation substrates
- - Chun-Yung Sung
  - Haizhou Yin
  - et al.
- 2005
- IEDM 2005
Conference paper
Selective epitaxial channel ground plane thin SOI CMOS devices
- - Zhibin Ren
  - M. Ieong
  - et al.
- 2005
- IEDM 2005
Conference paper
Synthesis and control of ultra thin gate oxides for the 90 and 65 NM nodes
- - Joseph F. Shepard Jr.
  - Anthony Chou
  - et al.
- 2005
- RTP 2005
Conference paper
65nm CMOS technology for low power applications
- - A. Steegen
  - R. Mo
  - et al.
- 2005
- IEDM 2005
Conference paper