Performance analysis and modeling of deep trench decoupling capacitor for 32 nm high-performance SOI processors and beyond
- Balaji Jayaraman
- Sneha Gupta
- et al.
- 2012
- ICICDT 2012
Conference paper
Publications
13 results for Sadanand Deshpande
Chip-level power-performance optimization through thermally-driven across-chip variation (ACV) reduction
- X. Yu
- Oleg Gluschenkov
- et al.
- 2011
- IEDM 2011
Conference paperCharacterization of novel TiN/HfO2 metal insulator semiconductor stack for 32nm eDRAM
- Puneet Goyal
- Sneha Gupta
- et al.
- 2010
- IEEE International SOI Conference 2010
Conference paperAdvanced junction formation for Sub-32nm logic devices
- Sadanand V. Deshpande
- Ahmet Ozcan
- et al.
- 2010
- IWJT 2010
Conference paperReduction of RTA-driven intra-die variation via model-based layout optimization
- J.C. Scott
- O. Gluschenkov
- et al.
- 2009
- VLSI Technology 2009
Conference paperA 45nm low power bulk technology featuring carbon co-implantation and laser anneal on 45°-rotated substrate
- J. Yuan
- V. Chan
- et al.
- 2008
- ICSICT 2008
Conference paperImproving the power-performance of multicore processors through optimization of lithography and thermal processing
- A. Gabor
- T.A. Brunner
- et al.
- 2007
- SPIE Advanced Lithography 2007
Conference paperImplementation of robust nickel alloy salicide process for high-performance 65nm SOI CMOS manufacturing
- Jay Strane
- David Brown
- et al.
- 2007
- VLSI-TSA 2007
Conference paperRTA-driven intra-die variations in stage delay, and parametric sensitivities for 65nm technology
- I. Ahsan
- N. Zamdmer
- et al.
- 2006
- VLSI Technology 2006
Conference paperLower resistance scaled metal contacts to silicide for advanced CMOS
- A. Topol
- C. Sheraw
- et al.
- 2006
- VLSI Technology 2006
Conference paper