Patterning strategies for gate level tip-tip distance reduction in SRAM cell for 45nm and beyond
- Haoren Zhuang
- Helen Wang
- et al.
- 2007
- ISTC 2007
Conference paper
Publications
24 results for N. Rovedo
A 45nm low cost low power platform by using integrated dual-stress-liner technology
- J. Yuan
- S.S. Tan
- et al.
- 2006
- VLSI Technology 2006
Conference paperNovel enhanced stressor with graded embedded SiGe source/drain for high performance CMOS devices
- J.-P. Han
- H. Utomo
- et al.
- 2006
- IEDM 2006
Conference paperDirect silicon bonded (DSB) substrate solid phase epitaxy (SPE) integration scheme study for high performance bulk CMOS
- Haizhou Yin
- C.Y. Sung
- et al.
- 2006
- IEDM 2006
Conference paperProcess induced stress for CMOS performance improvement
- S. Fang
- S.S. Tan
- et al.
- 2006
- ICSICT 2006
Conference paperInvestigation of CMOS devices with embedded SiGe source/drain on hybrid orientation substrates
- Qiqing Ouyang
- Min Yang
- et al.
- 2005
- VLSI Technology 2005
Conference paperInteraction of middle-of-line (MOL) temperature and mechanical stress on 90nm hi-speed device performance and reliability
- K.Y. Lim
- V. Chan
- et al.
- 2005
- ESSDERC 2005
Conference paperDesign of high performance PFETs with strained Si channel and laser anneal
- Z. Luo
- Y.F. Chong
- et al.
- 2005
- IEDM 2005
Conference paperHigh performance CMOS bulk technology using direct silicon bond (DSB) mixed crystal orientation substrates
- Chun-Yung Sung
- Haizhou Yin
- et al.
- 2005
- IEDM 2005
Conference paperOn the integration of CMOS with hybrid crystal orientations
- M. Yang
- V. Chan
- et al.
- 2004
- VLSI Technology 2004
Conference paper