Chip-level power-performance optimization through thermally-driven across-chip variation (ACV) reduction
- X. Yu
- Oleg Gluschenkov
- et al.
- 2011
- IEDM 2011
Conference paper
Publications
19 results for A.C. Mocuta
Novel high-performance analog devices for advanced low-power high-k metal gate complementary metal-oxide-semiconductor technology
- Jin-Ping Han
- Takashi Shimizu
- et al.
- 2011
- Japanese Journal of Applied Physics
PaperReverse temperature dependence of circuit performance in high- k/metal-gate technology
- Shu-Jen Han
- Dechao Guo
- et al.
- 2009
- IEEE Electron Device Letters
PaperReduction of RTA-driven intra-die variation via model-based layout optimization
- J.C. Scott
- O. Gluschenkov
- et al.
- 2009
- VLSI Technology 2009
Conference paperTechnology elements of a common platform bulk foundry offering (invited)
- P. Gilbert
- A. Steegen
- et al.
- 2007
- IEDM 2007
Conference paperDirect temperature measurement for VLSI circuits and 3-D modeling of self-heating in sub-0.13 μm SOI technologies
- R.V. Joshi
- S.S. Kang
- et al.
- 2005
- VLSID 2005
Conference paperHigh performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell
- E. Leobandung
- H. Nayakama
- et al.
- 2005
- VLSI Technology 2005
Conference paperRetardation of arsenic diffusion in silicon-germanium by co-implantation
- Omer Dokumaci
- Paul Ronsheim
- et al.
- 2004
- ECS Meeting 2004
Conference paperPerformance comparison and channel length scaling of strained Si FETs on SiGe-on-insulator (SGOI)
- J. Cai
- K. Rim
- et al.
- 2004
- IEDM 2004
Conference paperBody voltage and history effect sensitivity to key device parameters in 90nm PD-SOI
- S. Kawanaka
- M.B. Ketchen
- et al.
- 2004
- IEEE International SOI Conference 2004
Conference paper