A robust reliability methodology for accurately predicting Bias Temperature Instability induced circuit performance degradation in HKMG CMOS
- D.P. Ioannou
- K. Zhao
- et al.
- 2011
- IRPS 2011
Conference paper
Publications
20 results for K. Das
Yield estimation of SRAM circuits using "Virtual SRAM Fab"
- Aditya Bansal
- Rama N. Singh
- et al.
- 2009
- ICCAD 2009
Conference paperVariability and power management in sub-100nm SOI technology for reliable high performance systems
- Koushik Das
- Kerry Bernstein
- et al.
- 2008
- IEEE International SOI Conference 2008
Conference paperCMOS latch metastability characterization at the 65-nm-technology node
- Manjul Bhushan
- Mark B. Ketchen
- et al.
- 2008
- ICMTS 2008
Conference paperUltra-low leakage MTCMOS circuits with regular-Vt long channel stacked footers for deep sub-100 nm technologies
- Koushik K. Das
- Ching-Te Chuang
- 2008
- VLSI-DAT 2008
Conference paperReducing parasitic BJT effects in partially depleted SOI digital logic circuits
- Koushik K. Das
- Ching-Te Chuang
- et al.
- 2008
- Microelectronics Journal
PaperPower-gating schemes for Ultra-Thin SOI (UTSOI) circuits in hybrid SOI-epitaxial CMOS structures
- Shih-Hsien Lo
- Koushik K. Das
- et al.
- 2007
- VLSI-DAT 2007
Conference paperNovel high-density data-retention power gating structure using a four-terminal double-gate device
- Keunwoo Kim
- Koushik K. Das
- et al.
- 2007
- VLSI-DAT 2007
Conference paperHigh-density data-retention power gating structure using a four-terminal double-gate device
- K. Kim
- K. Das
- et al.
- 2007
- International Journal of Electronics
PaperAn integrated CAD methodology for evaluating MOSFET and parasitic extraction models and variability
- K. Koushik Das
- Steven G. Walker
- et al.
- 2007
- Proceedings of the IEEE
Paper