A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology
- Timothy O. Dickson
- Yong Liu
- et al.
- 2014
- CICC 2014
Conference paper
Publications
27 results for Mark Ferriss
A 46.4-58.1 GHz frequency synthesizer featuring a 2nd harmonic extraction technique that preserves VCO performance
- Bodhisatwa Sadhu
- Mark Ferriss
- et al.
- 2014
- RFIC 2014
Conference paperIndirect performance sensing for on-chip self-healing of analog and RF circuits
- Shupeng Sun
- Fa Wang
- et al.
- 2014
- IEEE TCAS-I
PaperA 28 GHz hybrid PLL in 32 nm SOI CMOS
- Mark Ferriss
- Alexander Rylyakov
- et al.
- 2014
- IEEE JSSC
PaperIndirect performance sensing for on-chip analog self-healing via Bayesian model fusion
- S. Sun
- F. Wang
- et al.
- 2013
- CICC 2013
Conference paperA 28GHz hybrid PLL in 32nm SOI CMOS
- Mark Ferriss
- Alexander Rylyakov
- et al.
- 2013
- VLSI Circuits 2013
Conference paperA fully-integrated dual-polarization 16-element W-band phased-array transceiver in SiGe BiCMOS
- Alberto Valdes-Garcia
- Arun Natarajan
- et al.
- 2013
- RFIC 2013
Conference paperA 73.9-83.5GHz synthesizer with -111dBc/Hz phase noise at 10MHz offset in a 130nm SiGe BiCMOS technology
- Jean-Olivier Plouchart
- Mark Ferriss
- et al.
- 2013
- RFIC 2013
Conference paperA linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing
- Bodhisatwa Sadhu
- Mark A. Ferriss
- et al.
- 2013
- IEEE JSSC
PaperAn integral path self-calibration scheme for a dual-loop PLL
- Mark Ferriss
- Jean-Olivier Plouchart
- et al.
- 2013
- IEEE JSSC
Paper