A 250-mW 60-GHz CMOS Transceiver SoC Integrated with a Four-Element AiP Providing Broad Angular Link Coverage
- Bodhisatwa Sadhu
- Alberto Valdes-Garcia
- et al.
- 2020
- IEEE JSSC
Paper
Publications
27 results for Mark Ferriss
A Software-Defined Phased Array Radio with mmWave to Software Vertical Stack Integration for 5G Experimentation
- Bodhisatwa Sadhu
- Arun Paidimarri
- et al.
- 2018
- IMS 2018
Conference paperA gradient descent bias optimizer for oscillator phase noise reduction demonstrated in 45nm and 32nm SOI CMOS
- Mark Ferriss
- Bodhisatwa Sadhu
- et al.
- 2018
- RFIC 2018
Conference paperA 28-GHz 32-Element TRX Phased-Array IC with Concurrent Dual-Polarized Operation and Orthogonal Phase and Gain Control for 5G Communications
- Bodhisatwa Sadhu
- Yahya Tousi
- et al.
- 2017
- IEEE JSSC
PaperA 60GHz packaged switched beam 32nm CMOS TRX with broad spatial coverage, 17.1dBm peak EIRP, 6.1dB NF at < 250mW
- Bodhisatwa Sadhu
- Alberto Valdes-Garcia
- et al.
- 2016
- RFIC 2016
Conference paperA 12-to-26GHz fractional-N PLL with dual continuous tuning LC-D/VCOs
- Mark Ferriss
- Bodhisatwa Sadhu
- et al.
- 2016
- ISSCC 2016
Conference paperA capacitance boosted full-octave LC VCO based 0.7 to 24 GHz fractional-N synthesizer
- Bodhisatwa Sadhu
- Mark Ferriss
- et al.
- 2015
- RFIC 2015
Conference paperA 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology
- Timothy O. Dickson
- Yong Liu
- et al.
- 2015
- IEEE JSSC
PaperA 52 GHz frequency synthesizer featuring a 2nd harmonic extraction technique that preserves VCO performance
- Bodhisatwa Sadhu
- Mark Ferriss
- et al.
- 2015
- IEEE JSSC
PaperA 13.1-to-28GHz fractional-N PLL in 32nm SOI CMOS with a ΔΣ noise-cancellation scheme
- Mark Ferriss
- Bodhisatwa Sadhu
- et al.
- 2015
- ISSCC 2015
Conference paper