A 45nm low cost low power platform by using integrated dual-stress-liner technology
- J. Yuan
- S.S. Tan
- et al.
- 2006
- VLSI Technology 2006
Conference paper
Publications
13 results at VLSI Technology 2006
Investigation of FinFET devices for 32nm technologies and beyond
- H. Shang
- L. Chang
- et al.
- 2006
- VLSI Technology 2006
Conference paperA new route to ultra-high density memory using the Micro to Nano Addressing Block (MNAB)
- R.S. Shenoy
- K. Gopalakrishnan
- et al.
- 2006
- VLSI Technology 2006
Conference paperNovel one-mask self-heating pillar phase change memory
- T.D. Happ
- M. Breitwisch
- et al.
- 2006
- VLSI Technology 2006
Conference paperStress proximity technique for performance improvement with dual stress liner at 45nm technology and beyond
- X. Chen
- S. Fang
- et al.
- 2006
- VLSI Technology 2006
Conference paperIntegration of local stress techniques with strained-Si directly on insulator (SSDOI) substrates
- Haizhou Yin
- Z. Ren
- et al.
- 2006
- VLSI Technology 2006
Conference paperNovel approach to reduce source/drain series resistance in high performance CMOS devices using self-aligned CoWP process for 45nm node UTSOI transistors with 20nm gate length
- James Pan
- Anna Topol
- et al.
- 2006
- VLSI Technology 2006
Conference paperSilicon-on-insulator MOSFETs with hybrid crystal orientations
- M. Yang
- K.K. Chan
- et al.
- 2006
- VLSI Technology 2006
Conference paperLower resistance scaled metal contacts to silicide for advanced CMOS
- A. Topol
- C. Sheraw
- et al.
- 2006
- VLSI Technology 2006
Conference paperBand-edge high-performance high-κ /metal gate n-MOSFETs using cap layers containing group IIA and IIIB elements with gate-first processing for 45 nm and beyond
- V. Narayanan
- V.K. Paruchuri
- et al.
- 2006
- VLSI Technology 2006
Conference paper