CONSIDERING TIMING CONSTRAINTS IN SYNTHESIS FROM A BEHAVIOURAL DESCRIPTION.Raul CamposanoArno Kunzmann1985ICCD 1985
SWITCH-LEVEL SIMULATION FOR MEMORY MAPPED GENERAL PURPOSE PARALLEL PROCESSORS.D. BeeceJ. Gorenet al.1985ICCD 1985
PARALLELIZING CIRCUIT SIMULATION USING A COMBINED ALGORITHMIC AND SPECIALIZED HARDWARE APPROACH.J. WhiteNicholas Weiner1985ICCD 1985
DESIGN OPTIMIZATION FOR CONTROL CIRCUITS IMPLEMENTED WITH PLAS.H.H. ChaoShauchi Onget al.1985ICCD 1985