C.T. Chuang, P.F. Lu, et al.
VLSI-TSA 1997
The Letter describes the first experimental result of a high-speed low-power ECL-based AC-coupled complementary push-pull circuit. Implemented in a 0.8µm high-performance fully complementary bipolar technology with 50GHz npn transistor and 13GHz pnp transistor, a power-delay product of 34fJ (23.2ps at 1.48mW) has been achieved compared with 67 fJ (45 ps at 1.48mW) for the npn-only ECL circuit. © 1993, The Institution of Electrical Engineers. All rights reserved.
C.T. Chuang, P.F. Lu, et al.
VLSI-TSA 1997
J.H. Comfort, P.F. Lu, et al.
VLSI Technology 1990
Satish Kumar, Rajiv V. Joshi, et al.
ICICDT 2007
J. Warnock, Brian Curran, et al.
ISSCC 2015