Latch design techniques for mitigating single event upsets in 65 nm SOI device technology

A.J. KleinOsowski; Ethan H. Cannon; Michael S. Gordon; David F. Heidel; Phil Oldiges; Cristina Plettner; Kenneth P. Rodbell; Ronald D. Rose; Henry H. K. Tang

doi:10.1109/TNS.2007.909707

IEEE TNS

Paper

01 Dec 2007

Latch design techniques for mitigating single event upsets in 65 nm SOI device technology

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Abstract

This paper describes techniques for mitigating single event upsets in master-slave flip-flop latches in 65 nm SOI device technology. Techniques are explained, modeled, and measured with hardware experiments. © 2007 IEEE.

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