Gate length and performance scaling of undoped-body extremely thin SOI MOSFETs
- Amlan Majumdar
- Xinlin Wang
- et al.
- 2009
- IEEE Electron Device Letters
Paper
Publications
18 results for David Dobuzinsky
High-performance undoped-body 8-nm-thin SOI field-effect transistors
- Amlan Majumdar
- Zhibin Ren
- et al.
- 2008
- IEEE Electron Device Letters
PaperUltra-low leakage silicon-on-insulator technology for 65 nm node and beyond
- Jin Cai
- Amlan Majumdar
- et al.
- 2007
- IEDM 2007
Conference paperA 0.127 μm2 high performance 65 nm SOI based embedded DRAM for on-processor applications
- G. Wang
- K. Cheng
- et al.
- 2006
- IEDM 2006
Conference paperUltra-thin SOI replacement gate CMOS with ALD TaN / high-k gate stack
- B. Doris
- B.P. Linder
- et al.
- 2005
- VLSI-TSA 2005
Conference paperDevice Design Considerations for Ultra-Thin SOI MOSFETs
- B. Doris
- M. Ieong
- et al.
- 2003
- IEDM 2003
Conference paperStructural demonstration of cost effective Isolation Trench fill for sub-110nm vertical trench DRAM and SOC applications
- S.-W. Yang
- W.-S. Liao
- et al.
- 2003
- VLSI-TSA 2003
Conference paperHigh yielding self-aligned contact-process for a 0.150-μm DRAM technology
- Thomas S. Rupp
- David Dobuzinsky
- et al.
- 2002
- IEEE Trans Semicond Manuf
PaperA contact-reducing method over topography by combining the RELACS technique and bi-layer process
- Chieh-Yu Lin
- Karen Petrillo
- et al.
- 2002
- Proceedings of SPIE - The International Society for Optical Engineering
PaperAluminum dual damascene metallization for 0.175 μm DRAM generations and beyond
- R.F. Schnabel
- L. Clevenger
- et al.
- 2000
- Microelectronic Engineering
Paper