Lithography and fabrication processes for sub-100 nm scale complementary metal-oxide semiconductor
- S.J. Wind
- Y. Taur
- et al.
- 1995
- Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures
Paper
Publications
14 results for Y. Mii
Probing the limits of silicon-based nanoelectronics
- S.J. Wind
- Y. Taur
- et al.
- 1995
- MRS Spring Meeting 1995
Conference paperVLSI on-chip interconnection performance simulations and measurements
- D. Edelstein
- G.A. Sai-Halasz
- et al.
- 1995
- IBM J. Res. Dev
PaperCMOS scaling into the 21st century: 0.1 μm and beyond
- Y. Taur
- Y. Mii
- et al.
- 1995
- IBM J. Res. Dev
PaperOn “Effective Channel Length” in 0.1-µm MOSFET's
- Yuan Taur
- Yuh-Jier Mii
- et al.
- 1995
- IEEE Electron Device Letters
PaperUltra-low power 0.1 μm CMOS
- Y. Mii
- S.J. Wind
- et al.
- 1994
- VLSI Technology 1994
Conference paperExperimental High Performance Sub-0.1 μm Channel nMOSFET's
- Y. Mii
- S. Rishton
- et al.
- 1994
- IEEE Electron Device Letters
PaperHigh Performance 0.1 μm CMOS Devices with 1.5 V Power Supply
- Y. Taur
- S.J. Wind
- et al.
- 1993
- IEDM 1993
Conference paperPerformance consideration for the scaling of sub-micron on-chip interconnections
- Yuh-Jier Mii
- 1992
- SPIE Microelectronic Processing 1992
Conference paperHigh performance 0.1μm nMOSFET's with 10 ps/stage delay (85 K) at 1.5 V power supply
- Y. Mii
- S. Rishton
- et al.
- 1993
- VLSI Technology 1993
Conference paper