A 1.8 pJ/bit 16 × 16Gb/s source-synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration
- Timothy O. Dickson
- Yong Liu
- et al.
- 2016
- IEEE JSSC
Paper
Publications
25 results for Yong Liu
A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI
- Sergey V. Rylov
- Troy Beukema
- et al.
- 2016
- ISSCC 2016
Conference paperA 1.8-pJ/bit 16x16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration
- Timothy O. Dickson
- Yong Liu
- et al.
- 2015
- CICC 2015
Conference paperA 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology
- Timothy O. Dickson
- Yong Liu
- et al.
- 2015
- IEEE JSSC
PaperA 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology
- Timothy O. Dickson
- Yong Liu
- et al.
- 2014
- CICC 2014
Conference paperCharacterization of TSV-induced loss and substrate noise coupling in advanced three-dimensional CMOS SOI technology
- Xiaoxiong Gu
- Joel A. Silberman
- et al.
- 2013
- IEEE Transactions on CPMT
PaperA 60GHz, linear, direct down-conversion mixer with mm-Wave tunability in 32nm CMOS SOI
- Mihai Sanduleanu
- Alberto Valdes-Garcia
- et al.
- 2013
- CICC 2013
Conference paperA 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI
- Yong Liu
- Ping-Hsuan Hsieh
- et al.
- 2013
- ISSCC 2013
Conference paperSmall NMR biomolecular sensors
- Nan Sun
- Yong Liu
- et al.
- 2013
- Solid-State Electronics
PaperSpecifications of nanoscale devices and circuits for neuromorphic computational systems
- Bipin Rajendran
- Yong Liu
- et al.
- 2013
- IEEE T-ED
Paper