Mitigating X‑ray–Induced Damage in CD‑SAXS Metrology of EUV Resists
- Philipp Wieser
- Kevin Yager
- et al.
- 2026
- SPIE Advanced Lithography + Patterning 2026
Conference paper
Publications
24 results for Logic Scaling
Exploring the Limits of Contact Hole Patterning with High NA EUV Lithography
- Dario Goldfarb
- Zheng Chen
- et al.
- 2026
- SPIE Advanced Lithography + Patterning 2026
TalkBlock-Level Design Optimization for Sub-100-nm Cell Height Libraries with Stacked Transistor
- Nick Lanzillo
- Jim Mazza
- et al.
- 2025
- IEDM 2025
Conference paperSiGe Channel for Scaled Gate-All-Around Nanosheet pFET Transistor for Advanced Logic Applications
- Shogo Mochizuki
- Sushant Kumar
- et al.
- 2025
- IEDM 2025
Conference paper28P L/S Dry Resist Process Flow Co-optimization at Low NA EUV
- Chun-chia Brown Lu
- Saumya Gulati
- et al.
- 2025
- ANS 2025
PosterDose reduction strategies for low-n PSM absorber using pupil and mask bias optimization at 0.33NA EUV lithography
- Rajiv Sejpal
- Gopal Kenath
- et al.
- 2025
- Photomask Japan 2025
Conference paperIn-Line Metrology for Sub-2nm Technology Nodes
- Daniel Schmidt
- 2025
- PMI Symposium 2025
Invited talkOptimization of 3nm High Performance Nanosheet Technology for 77 K Operation
- Julien Frougier
- Ruqiang Bao
- et al.
- 2025
- GOMACTech 2025
Conference paperEvaluating Novel Material Stacks Towards Gate Width Roughness Reduction
- Gopal Kenath
- Martin Burkhardt
- et al.
- 2025
- SPIE Advanced Lithography + Patterning 2025
Conference paperAccelerating High NA EUV Lithography Insertion for Interconnect Scaling and Beyond: Performance, Cost, and Future Prospects
- Luciana Meli
- Indira Seshadri
- et al.
- 2025
- SPIE Advanced Lithography + Patterning 2025
Conference paper