Reliability Challenges of Emerging Transistor Materials and Architectures Beyond Traditional Scaling

Introduction: As conventional transistor scaling approaches its physical and economic limits, the industry is rapidly exploring a diverse set of new materials and novel device architectures to meet future demands for performance, power efficiency, and integration density. While these innovations—such as vertical-channel FETs, CFETs, 3D stacked transistors, layout-optimized technologies (Forksheet, DTCO), and materials-driven devices (e.g., SiGe, germanium, amorphous oxide semiconductors, 2D materials, CNT, HfZrO2)—offer promising breakthroughs, they also introduce unprecedented reliability challenges. This workshop will focus exclusively on the reliability aspects of these emerging transistor technologies, providing a forum to discuss failure mechanisms, modeling complexities, and qualification strategies necessary to ensure robust deployment in advanced systems.

Proposed topics include, but are not limited to: Design and reliability implications of vertical-channel, CFET, and 3D stacked transistor architectures. Material-specific reliability concerns, including defect generation, thermal instability, and long-term degradation and correlated electron systems. Reliability modeling and assessment methodologies tailored to unconventional materials and structures. Design-Technology Co-Optimization (DTCO) strategies to mitigate reliability risks in layout-constrained and stacked transistor designs. Test and qualification approaches for emerging devices under realistic mission profiles and environmental conditions.