Block-Level Design Optimization for Sub-100-nm Cell Height Libraries with Stacked Transistor
- Nick Lanzillo
- Jim Mazza
- et al.
- 2025
- IEDM 2025
Conference paper
Publications
11 results at IEDM 2025
Towards Scalable 3D Integration of 2T-nC FeRAM with Hundreds of Layer Stacking
- Jiahui Duan
- Shan Deng
- et al.
- 2025
- IEDM 2025
Conference paperPhysical Computing with Coupled Oscillators – Current Progress and Future Directions
- Aida Todri-sanial
- Jelle Verest
- et al.
- 2025
- IEDM 2025
Conference paperProgress and Gaps in Double Spin-torque MTJs for Last Level Cache Applications
- Guohan Hu
- Philip Trouilloud
- et al.
- 2025
- IEDM 2025
Conference paperSiGe Channel for Scaled Gate-All-Around Nanosheet pFET Transistor for Advanced Logic Applications
- Shogo Mochizuki
- Sushant Kumar
- et al.
- 2025
- IEDM 2025
Conference paperA Novel A-IMC Ge-GST ePCM Cell for Edge AI Applications on 28nm FD-SOI Platform
- Matteo Baldo
- Mario Allegra
- et al.
- 2025
- IEDM 2025
Short paperDisc-type Phase-change Memory Devices for Analog In-memory Computing
- 2025
- IEDM 2025
Short paperTransfer Learning on Edge Using 14nm CMOS-compatible ReRAM Array and Analog In-memory Training Algorithm
- Takashi Ando
- Omobayode Fagbohungbe
- et al.
- 2025
- IEDM 2025
Invited talkCo-packaged optics module with single mode polymer waveguide
- Akihiro Horibe
- Yoichi Taira
- et al.
- 2025
- IEDM 2025
Invited talkEnabling Enterprise AI with IBM Spyre
- Jeffrey Burns
- Leland Chang
- et al.
- 2025
- IEDM 2025
Invited talk